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[/] [spi_master_slave/] [trunk/] [syn/] [ATLYS_05.SET] - Rev 22

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22 spi_slave.vhd: v2.02.0126 [JD]
ISSUE: the miso_o MUX that preloads tx_bit when SSEL='1' will glitch for CPHA='1'.
FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update.
jdoin 3266d 17h /spi_master_slave/trunk/syn/ATLYS_05.SET

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