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[/] [spi_master_slave/] [trunk/] [syn/] [grp_debouncer.vhd] - Rev 24

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24 - fixed range of the switch debouncer for the verification circuit
- reorganized rtl folder in mainstream trunk
jdoin 3244d 06h /spi_master_slave/trunk/syn/grp_debouncer.vhd
23 Clarified copyright and licensing
Added trunk/license directory
Added LGPL 3.0 license text "lgpl.txt"
Fixed inline url for the GNU link of the LGPL license
Updated readme files and rtl files
jdoin 3264d 11h /spi_master_slave/trunk/syn/grp_debouncer.vhd
12 SPI_SLAVE: v2.00.0110 [JD] FIX: CPHA bugs:
-- - redesigned core clocking to address all CPOL and CPHA configurations.
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
-- clock phases from SHIFT_EDGE.
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
jdoin 3296d 20h /spi_master_slave/trunk/syn/grp_debouncer.vhd
10 v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.
jdoin 3308d 20h /spi_master_slave/trunk/syn/grp_debouncer.vhd
7 Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. jdoin 3312d 22h /spi_master_slave/trunk/syn/grp_debouncer.vhd
5 Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
jdoin 3314d 20h /spi_master_slave/trunk/syn/grp_debouncer.vhd

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