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[/] [spi_master_slave/] [trunk/] [syn/] [grp_debouncer.vhd] - Rev 10

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10 v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.
jdoin 3427d 23h /spi_master_slave/trunk/syn/grp_debouncer.vhd
7 Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. jdoin 3432d 01h /spi_master_slave/trunk/syn/grp_debouncer.vhd
5 Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
jdoin 3433d 22h /spi_master_slave/trunk/syn/grp_debouncer.vhd

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