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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_test.vhd] - Rev 24

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Rev Log message Author Age Path
24 - fixed range of the switch debouncer for the verification circuit
- reorganized rtl folder in mainstream trunk
jdoin 3245d 17h /spi_master_slave/trunk/syn/spi_master_atlys_test.vhd
22 spi_slave.vhd: v2.02.0126 [JD]
ISSUE: the miso_o MUX that preloads tx_bit when SSEL='1' will glitch for CPHA='1'.
FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update.
jdoin 3267d 09h /spi_master_slave/trunk/syn/spi_master_atlys_test.vhd
20 - removed folder trunk/bench.
- added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores.
jdoin 3285d 10h /spi_master_slave/trunk/syn/spi_master_atlys_test.vhd
13 spi_slave.vhd: v2.02.0120
spi_master.vhd: v1.15.0135

Several bugs fixed. Master and Slave cores tested at all spi modes, at 50MHz SCK, including continuous transfers.
jdoin 3294d 07h /spi_master_slave/trunk/syn/spi_master_atlys_test.vhd
12 SPI_SLAVE: v2.00.0110 [JD] FIX: CPHA bugs:
-- - redesigned core clocking to address all CPOL and CPHA configurations.
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
-- clock phases from SHIFT_EDGE.
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
jdoin 3298d 07h /spi_master_slave/trunk/syn/spi_master_atlys_test.vhd

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