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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_summary.html] - Rev 20

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20 - removed folder trunk/bench.
- added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores.
jdoin 3369d 19h /spi_master_slave/trunk/syn/spi_master_summary.html

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