OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [spi_test_ct.wcfg] - Rev 24

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 - fixed range of the switch debouncer for the verification circuit
- reorganized rtl folder in mainstream trunk
jdoin 3245d 17h /spi_master_slave/trunk/syn/spi_test_ct.wcfg
20 - removed folder trunk/bench.
- added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores.
jdoin 3285d 10h /spi_master_slave/trunk/syn/spi_test_ct.wcfg
13 spi_slave.vhd: v2.02.0120
spi_master.vhd: v1.15.0135

Several bugs fixed. Master and Slave cores tested at all spi modes, at 50MHz SCK, including continuous transfers.
jdoin 3294d 07h /spi_master_slave/trunk/syn/spi_test_ct.wcfg

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.