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[/] [spi_master_slave] - Rev 8

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8 Updated Documentation jdoin 4760d 19h /spi_master_slave
7 Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. jdoin 4761d 09h /spi_master_slave
6 v1.10.0075: Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
jdoin 4763d 06h /spi_master_slave
5 Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
jdoin 4763d 06h /spi_master_slave
4 v0.97.0068 - streamlined resets and clock enables to reduce area
v0.97.0075 - redesigned parallel interfaces, with pipelined data transport for async clock domains
v0.97.0083 - fixed bug "CPHA effect": redesigned SCK output circuit
v0.97.0086 - removed master MISO input register: got 33MHz.
jdoin 4788d 07h /spi_master_slave
3 - fixed fsm async glitches at state changes
- changed async clears to sync resets
- improved idle state logic for parallel interface
- added cross-clock register buffers
- exposed internal state and nets for debug
jdoin 4797d 05h /spi_master_slave
2 v0.95.0050 - Master/Slave loopback verified at 25MHz. jdoin 4805d 10h /spi_master_slave
1 The project and the structure was created root 4819d 05h /spi_master_slave

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