URL https://opencores.org/ocsvn/spi_slave/spi_slave/trunk

Subversion Repositories spi_slave

[/] [spi_slave/] [trunk/] - Rev 38

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Rev	Log message	Author	Age	Path
38		dkoethe	5521d 13h	/spi_slave/trunk/
35	New directory structure.	root	5524d 01h	/spi_slave/trunk/
34	changed test TX-CRC Block from end of block to start change crc value eb99fa90 to e4ea78bf	dkoethe	5822d 14h	/trunk/
33	moved TX CRC Value from end of packet to the start.	dkoethe	5822d 14h	/trunk/
32	added: > lib opb_spi_slave_v1_00_a PCK_CRC32_D32.vhd vhdl > lib opb_spi_slave_v1_00_a crc_gen.vhd vhdl > lib opb_spi_slave_v1_00_a opb_spi_slave vhdl	dkoethe	5822d 16h	/trunk/
31	added PARAMETER C_CRC_EN = true, DT = BOOLEAN	dkoethe	5822d 16h	/trunk/
30	added doxygen comments	dkoethe	5822d 16h	/trunk/
29	Changed TX CRC-Calculation	dkoethe	5822d 16h	/trunk/
28	Changed TX CRC-Insertion	dkoethe	5822d 16h	/trunk/
27	added test for CRC	dkoethe	5874d 15h	/trunk/
26	Initial Release	dkoethe	5874d 15h	/trunk/
25	added > vcom -93 ../../../../../rtl/vhdl/PCK_CRC8_D8.vhd > vcom -93 ../../../../../rtl/vhdl/PCK_CRC32_D32.vhd > vcom -93 ../../../../../rtl/vhdl/crc_gen.vhd > vcom -93 ../../../../../rtl/vhdl/crc_core.vhd	dkoethe	5874d 15h	/trunk/
24	added Register C_ADR_RX_CRC. C_ADR_TX_CRC	dkoethe	5874d 15h	/trunk/
23	added logic for CRC-Generation	dkoethe	5874d 15h	/trunk/
22	added signal opb_m_last_block for CRC	dkoethe	5874d 15h	/trunk/
21	added constant C_ADR_RX_CRC,C_ADR_TX_CRC, added constant C_OPB_CTL_REG_CRC_EN, C_OPB_CTL_REG_CRC_CLR	dkoethe	5874d 15h	/trunk/
20	Initial Release	dkoethe	5874d 15h	/trunk/
19	Version 1.2 removed delays for simulation	dkoethe	5979d 14h	/trunk/
18	Version 1.1 Bugfix added syncronisation registers opb_fifo_flg_int_r[0,1] to prevent metastability	dkoethe	5979d 14h	/trunk/
17	no message	dkoethe	5986d 11h	/trunk/

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Subversion Repositories spi_slave

[/] [spi_slave/] [trunk/] - Rev 38

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