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Rev Log message Author Age Path
37 remove project zero_gravity 731d 04h /
36 - sources of storm_extractor added zero_gravity 3976d 08h /
35 - fixed bug in SP write back of LDM operations
- fixed bug in opcode decoding of SWI instruction
- documentary update
zero_gravity 4355d 09h /
34 - bug fixed in carry-flag generation logic (not-carry = borrow flag)
- missing signal in STORM_TOP.vhd added
zero_gravity 4395d 20h /
33 - branch-and-exchange instruction (BX) support added
=> for BX Rn, where Rn(0) = '0', behavior like branch to address = Rn
=> for BX Rn, where Rn(0) = '1', triggering undefined instruction trap
zero_gravity 4402d 05h /
32 - bug-fix of block transfer operations
=> now fully ARM-compatible
zero_gravity 4403d 17h /
31 - small documentary edits
- CACHE.vhd modified for better synthesis results
- BUS_UNIT.vhd update to fulfill WB specs
zero_gravity 4406d 04h /
30 - minor edits in doc zero_gravity 4411d 04h /
29 - specific IO area is now auto protected
- Wishbone compatibility extended
- cache flush optimized
- accelerated bus cycles due to less overhead
zero_gravity 4412d 04h /
28 - bugfix in pipeline re-sync of d/i-cache
- optimized bus unit
- minor edits... ^^
zero_gravity 4423d 07h /
27 updated "sim" folder
- error in testbench environment
-> old components
-> weren't compatible to new core version anymore
=> FIXED! ;)
- thanks to Pratip Mukherjee
zero_gravity 4427d 06h /
26 bug fixes:
- change in priority for cache miss/dirty/io_access
- memory based pc modifications
- removed internal timer
zero_gravity 4428d 06h /
25 bug-fix in cache component:
-> error in cache page-access history manager
zero_gravity 4436d 14h /
24 - changed back to original oc svn folder structure
- bug-fix in documentary
- WB_ERR_I signal added to terminate wishbone bus access
- bug-fix: system mode register set and privs
zero_gravity 4437d 13h /
23 zero_gravity 4437d 13h /
22 changed back to original svn folder structure zero_gravity 4437d 14h /
21 smaller, faster, better ;)
* bug-fix: load-multiple instructions
* new cache-control system
* direct-accessible IO area can be specified
* extended demo implementation
zero_gravity 4444d 08h /
20 - update of data sheet -> note for system memory map layout and d-cache configuration zero_gravity 4460d 03h /
19 - simulation test bench added
- example for compatible wishbone fabric/SoC added
- block transfers from user bank updated
zero_gravity 4460d 07h /
18 makefile update to ensure no thumb code is generated zero_gravity 4465d 12h /

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