URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [doc/] - Rev 12

Rev	Log message	Author	Age	Path
12	Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.	motilito	4437d 14h	/uart2bus/trunk/doc/
8	Updated core description document to include Lattice device synthesis results.	motilito	4753d 19h	/uart2bus/trunk/doc/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5131d 05h	/uart2bus/trunk/doc/
2	Uploaded the initial project version.	motilito	5177d 13h	/uart2bus/trunk/doc/