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[/] [uart2bus/] [trunk/] [verilog/] - Rev 12


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Rev Log message Author Age Path
12 Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism. motilito 4115d 01h /uart2bus/trunk/verilog/
9 Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. motilito 4210d 02h /uart2bus/trunk/verilog/
4 Corrected some problems in the binary mode protocol test bench.
Updated documentation.
motilito 4808d 16h /uart2bus/trunk/verilog/
3 motilito 4854d 22h /uart2bus/trunk/verilog/
2 Uploaded the initial project version. motilito 4855d 00h /uart2bus/trunk/verilog/

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