URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart_parser.v] - Rev 12

Rev	Log message	Author	Age	Path
12	Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.	motilito	4437d 00h	/uart2bus/trunk/verilog/rtl/uart_parser.v
2	Uploaded the initial project version.	motilito	5176d 22h	/uart2bus/trunk/verilog/rtl/uart_parser.v