OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] - Rev 23

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
23 fixed port map error in async fifo 1r1w unneback 4876d 12h /
22 added binary counters unneback 4876d 17h /
21 reg -> wire in and or mux in logic unneback 4877d 13h /
20 naming convention vl_ unneback 4879d 00h /
19 naming convention vl_ unneback 4879d 00h /
18 naming convention vl_ unneback 4879d 00h /
17 unneback 4942d 14h /
16 converting utility for ROM unneback 4943d 01h /
15 added delay line unneback 4948d 21h /
14 reg -> wire for various signals unneback 4949d 03h /
13 cosmetic update unneback 4949d 04h /
12 added wishbone comliant modules unneback 4950d 00h /
11 async fifo simplex unneback 4950d 15h /
10 added dff_ce_clear unneback 4952d 14h /
9 added dff_ce_clear unneback 4952d 14h /
8 added dff_ce_clear unneback 4952d 14h /
7 mem update unneback 4952d 15h /
6 added library files unneback 4965d 15h /
5 memories added unneback 4965d 16h /
4 added counters unneback 4969d 19h /
3 various updates
counter added
unneback 4972d 15h /
2 initial check-in unneback 4973d 15h /
1 The project and the structure was created root 4978d 19h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.