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Rev Log message Author Age Path
34 added vl_mux2_andor and vl_mux3_andor unneback 3891d 18h /
33 updated wb3wb3_bridge unneback 3904d 20h /
32 added vl_pll for ALTERA (cycloneIII) unneback 3912d 06h /
31 sync FIFO updated unneback 3932d 01h /
30 updated counter for level1 and level2 function unneback 3932d 02h /
29 updated counter for level1 and level2 function unneback 3932d 02h /
28 added sync simplex FIFO unneback 3933d 03h /
27 added sync simplex FIFO unneback 3933d 03h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3933d 04h /
25 added sync FIFO unneback 3933d 18h /
24 added vl_dff_ce_set unneback 3935d 01h /
23 fixed port map error in async fifo 1r1w unneback 3935d 16h /
22 added binary counters unneback 3935d 21h /
21 reg -> wire in and or mux in logic unneback 3936d 17h /
20 naming convention vl_ unneback 3938d 04h /
19 naming convention vl_ unneback 3938d 04h /
18 naming convention vl_ unneback 3938d 05h /
17 unneback 4001d 18h /
16 converting utility for ROM unneback 4002d 05h /
15 added delay line unneback 4008d 02h /

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