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Rev Log message Author Age Path
34 added vl_mux2_andor and vl_mux3_andor unneback 3530d 03h /
33 updated wb3wb3_bridge unneback 3543d 05h /
32 added vl_pll for ALTERA (cycloneIII) unneback 3550d 15h /
31 sync FIFO updated unneback 3570d 11h /
30 updated counter for level1 and level2 function unneback 3570d 11h /
29 updated counter for level1 and level2 function unneback 3570d 11h /
28 added sync simplex FIFO unneback 3571d 12h /
27 added sync simplex FIFO unneback 3571d 12h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3571d 13h /
25 added sync FIFO unneback 3572d 03h /
24 added vl_dff_ce_set unneback 3573d 11h /
23 fixed port map error in async fifo 1r1w unneback 3574d 01h /
22 added binary counters unneback 3574d 07h /
21 reg -> wire in and or mux in logic unneback 3575d 03h /
20 naming convention vl_ unneback 3576d 14h /
19 naming convention vl_ unneback 3576d 14h /
18 naming convention vl_ unneback 3576d 14h /
17 unneback 3640d 03h /
16 converting utility for ROM unneback 3640d 14h /
15 added delay line unneback 3646d 11h /
14 reg -> wire for various signals unneback 3646d 16h /
13 cosmetic update unneback 3646d 18h /
12 added wishbone comliant modules unneback 3647d 14h /
11 async fifo simplex unneback 3648d 04h /
10 added dff_ce_clear unneback 3650d 03h /
9 added dff_ce_clear unneback 3650d 03h /
8 added dff_ce_clear unneback 3650d 03h /
7 mem update unneback 3650d 04h /
6 added library files unneback 3663d 05h /
5 memories added unneback 3663d 05h /

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