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Rev Log message Author Age Path
39 added simple port prio based wb arbiter unneback 4803d 12h /
38 updated andor mux unneback 4803d 12h /
37 corrected polynom with length 20 unneback 4809d 08h /
36 added generic andor_mux unneback 4810d 17h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4811d 04h /
34 added vl_mux2_andor and vl_mux3_andor unneback 4811d 04h /
33 updated wb3wb3_bridge unneback 4824d 06h /
32 added vl_pll for ALTERA (cycloneIII) unneback 4831d 16h /
31 sync FIFO updated unneback 4851d 11h /
30 updated counter for level1 and level2 function unneback 4851d 11h /
29 updated counter for level1 and level2 function unneback 4851d 11h /
28 added sync simplex FIFO unneback 4852d 13h /
27 added sync simplex FIFO unneback 4852d 13h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4852d 14h /
25 added sync FIFO unneback 4853d 04h /
24 added vl_dff_ce_set unneback 4854d 11h /
23 fixed port map error in async fifo 1r1w unneback 4855d 02h /
22 added binary counters unneback 4855d 07h /
21 reg -> wire in and or mux in logic unneback 4856d 03h /
20 naming convention vl_ unneback 4857d 14h /
19 naming convention vl_ unneback 4857d 14h /
18 naming convention vl_ unneback 4857d 14h /
17 unneback 4921d 04h /
16 converting utility for ROM unneback 4921d 15h /
15 added delay line unneback 4927d 12h /
14 reg -> wire for various signals unneback 4927d 17h /
13 cosmetic update unneback 4927d 18h /
12 added wishbone comliant modules unneback 4928d 14h /
11 async fifo simplex unneback 4929d 05h /
10 added dff_ce_clear unneback 4931d 04h /

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