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Rev Log message Author Age Path
48 wb updated unneback 4269d 06h /
47 added help program for LFSR counters unneback 4364d 09h /
46 updated parity unneback 4365d 11h /
45 updated timing in io models unneback 4367d 05h /
44 added target independet IO functionns unneback 4370d 05h /
43 added logic for parity generation and check unneback 4374d 08h /
42 updated mux_andor unneback 4378d 08h /
41 typo in registers.v unneback 4378d 09h /
40 new build environment with custom.v added as a result file unneback 4378d 10h /
39 added simple port prio based wb arbiter unneback 4379d 07h /
38 updated andor mux unneback 4379d 07h /
37 corrected polynom with length 20 unneback 4385d 03h /
36 added generic andor_mux unneback 4386d 12h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4386d 23h /
34 added vl_mux2_andor and vl_mux3_andor unneback 4386d 23h /
33 updated wb3wb3_bridge unneback 4400d 01h /
32 added vl_pll for ALTERA (cycloneIII) unneback 4407d 11h /
31 sync FIFO updated unneback 4427d 06h /
30 updated counter for level1 and level2 function unneback 4427d 06h /
29 updated counter for level1 and level2 function unneback 4427d 06h /
28 added sync simplex FIFO unneback 4428d 08h /
27 added sync simplex FIFO unneback 4428d 08h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4428d 09h /
25 added sync FIFO unneback 4428d 23h /
24 added vl_dff_ce_set unneback 4430d 06h /
23 fixed port map error in async fifo 1r1w unneback 4430d 21h /
22 added binary counters unneback 4431d 02h /
21 reg -> wire in and or mux in logic unneback 4431d 22h /
20 naming convention vl_ unneback 4433d 09h /
19 naming convention vl_ unneback 4433d 09h /

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