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[/] [versatile_library/] - Rev 27

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Rev Log message Author Age Path
27 added sync simplex FIFO unneback 4879d 20h /versatile_library/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4879d 21h /versatile_library/
25 added sync FIFO unneback 4880d 10h /versatile_library/
24 added vl_dff_ce_set unneback 4881d 18h /versatile_library/
23 fixed port map error in async fifo 1r1w unneback 4882d 09h /versatile_library/
22 added binary counters unneback 4882d 14h /versatile_library/
21 reg -> wire in and or mux in logic unneback 4883d 10h /versatile_library/
20 naming convention vl_ unneback 4884d 21h /versatile_library/
19 naming convention vl_ unneback 4884d 21h /versatile_library/
18 naming convention vl_ unneback 4884d 21h /versatile_library/
17 unneback 4948d 10h /versatile_library/
16 converting utility for ROM unneback 4948d 22h /versatile_library/
15 added delay line unneback 4954d 18h /versatile_library/
14 reg -> wire for various signals unneback 4954d 23h /versatile_library/
13 cosmetic update unneback 4955d 01h /versatile_library/
12 added wishbone comliant modules unneback 4955d 21h /versatile_library/
11 async fifo simplex unneback 4956d 12h /versatile_library/
10 added dff_ce_clear unneback 4958d 11h /versatile_library/
9 added dff_ce_clear unneback 4958d 11h /versatile_library/
8 added dff_ce_clear unneback 4958d 11h /versatile_library/
7 mem update unneback 4958d 12h /versatile_library/
6 added library files unneback 4971d 12h /versatile_library/
5 memories added unneback 4971d 13h /versatile_library/
4 added counters unneback 4975d 16h /versatile_library/
3 various updates
counter added		 unneback 4978d 11h /versatile_library/
2 initial check-in unneback 4979d 12h /versatile_library/
1 The project and the structure was created root 4984d 16h /versatile_library/

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