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[/] [versatile_library/] - Rev 29

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Rev Log message Author Age Path
29 updated counter for level1 and level2 function unneback 4879d 00h /versatile_library/
28 added sync simplex FIFO unneback 4880d 01h /versatile_library/
27 added sync simplex FIFO unneback 4880d 01h /versatile_library/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4880d 03h /versatile_library/
25 added sync FIFO unneback 4880d 16h /versatile_library/
24 added vl_dff_ce_set unneback 4882d 00h /versatile_library/
23 fixed port map error in async fifo 1r1w unneback 4882d 15h /versatile_library/
22 added binary counters unneback 4882d 20h /versatile_library/
21 reg -> wire in and or mux in logic unneback 4883d 16h /versatile_library/
20 naming convention vl_ unneback 4885d 03h /versatile_library/
19 naming convention vl_ unneback 4885d 03h /versatile_library/
18 naming convention vl_ unneback 4885d 03h /versatile_library/
17 unneback 4948d 16h /versatile_library/
16 converting utility for ROM unneback 4949d 04h /versatile_library/
15 added delay line unneback 4955d 00h /versatile_library/
14 reg -> wire for various signals unneback 4955d 05h /versatile_library/
13 cosmetic update unneback 4955d 07h /versatile_library/
12 added wishbone comliant modules unneback 4956d 03h /versatile_library/
11 async fifo simplex unneback 4956d 18h /versatile_library/
10 added dff_ce_clear unneback 4958d 17h /versatile_library/
9 added dff_ce_clear unneback 4958d 17h /versatile_library/
8 added dff_ce_clear unneback 4958d 17h /versatile_library/
7 mem update unneback 4958d 18h /versatile_library/
6 added library files unneback 4971d 18h /versatile_library/
5 memories added unneback 4971d 18h /versatile_library/
4 added counters unneback 4975d 22h /versatile_library/
3 various updates
counter added		 unneback 4978d 17h /versatile_library/
2 initial check-in unneback 4979d 18h /versatile_library/
1 The project and the structure was created root 4984d 22h /versatile_library/

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