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[/] [versatile_library/] - Rev 41

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21 reg -> wire in and or mux in logic unneback 4012d 19h /versatile_library/
20 naming convention vl_ unneback 4014d 06h /versatile_library/
19 naming convention vl_ unneback 4014d 06h /versatile_library/
18 naming convention vl_ unneback 4014d 06h /versatile_library/
17 unneback 4077d 20h /versatile_library/
16 converting utility for ROM unneback 4078d 07h /versatile_library/
15 added delay line unneback 4084d 04h /versatile_library/
14 reg -> wire for various signals unneback 4084d 09h /versatile_library/
13 cosmetic update unneback 4084d 10h /versatile_library/
12 added wishbone comliant modules unneback 4085d 06h /versatile_library/

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