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[/] [versatile_library/] - Rev 50

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Rev Log message Author Age Path
50 added WB_B4RAM with byte enable unneback 4713d 20h /versatile_library/
49 added WB_B4RAM with byte enable unneback 4713d 20h /versatile_library/
48 wb updated unneback 4720d 14h /versatile_library/
47 added help program for LFSR counters unneback 4815d 17h /versatile_library/
46 updated parity unneback 4816d 19h /versatile_library/
45 updated timing in io models unneback 4818d 13h /versatile_library/
44 added target independet IO functionns unneback 4821d 13h /versatile_library/
43 added logic for parity generation and check unneback 4825d 16h /versatile_library/
42 updated mux_andor unneback 4829d 16h /versatile_library/
41 typo in registers.v unneback 4829d 17h /versatile_library/
40 new build environment with custom.v added as a result file unneback 4829d 18h /versatile_library/
39 added simple port prio based wb arbiter unneback 4830d 15h /versatile_library/
38 updated andor mux unneback 4830d 15h /versatile_library/
37 corrected polynom with length 20 unneback 4836d 11h /versatile_library/
36 added generic andor_mux unneback 4837d 20h /versatile_library/
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4838d 07h /versatile_library/
34 added vl_mux2_andor and vl_mux3_andor unneback 4838d 07h /versatile_library/
33 updated wb3wb3_bridge unneback 4851d 09h /versatile_library/
32 added vl_pll for ALTERA (cycloneIII) unneback 4858d 19h /versatile_library/
31 sync FIFO updated unneback 4878d 14h /versatile_library/
30 updated counter for level1 and level2 function unneback 4878d 15h /versatile_library/
29 updated counter for level1 and level2 function unneback 4878d 15h /versatile_library/
28 added sync simplex FIFO unneback 4879d 16h /versatile_library/
27 added sync simplex FIFO unneback 4879d 16h /versatile_library/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4879d 17h /versatile_library/
25 added sync FIFO unneback 4880d 07h /versatile_library/
24 added vl_dff_ce_set unneback 4881d 14h /versatile_library/
23 fixed port map error in async fifo 1r1w unneback 4882d 05h /versatile_library/
22 added binary counters unneback 4882d 10h /versatile_library/
21 reg -> wire in and or mux in logic unneback 4883d 06h /versatile_library/

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