URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] - Rev 27

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Rev	Log message	Author	Age	Path
27	added sync simplex FIFO	unneback	4878d 01h	/versatile_library/trunk/rtl/
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4878d 03h	/versatile_library/trunk/rtl/
25	added sync FIFO	unneback	4878d 16h	/versatile_library/trunk/rtl/
24	added vl_dff_ce_set	unneback	4880d 00h	/versatile_library/trunk/rtl/
23	fixed port map error in async fifo 1r1w	unneback	4880d 15h	/versatile_library/trunk/rtl/
22	added binary counters	unneback	4880d 20h	/versatile_library/trunk/rtl/
21	reg -> wire in and or mux in logic	unneback	4881d 16h	/versatile_library/trunk/rtl/
18	naming convention vl_	unneback	4883d 03h	/versatile_library/trunk/rtl/
17		unneback	4946d 16h	/versatile_library/trunk/rtl/
15	added delay line	unneback	4953d 00h	/versatile_library/trunk/rtl/
14	reg -> wire for various signals	unneback	4953d 05h	/versatile_library/trunk/rtl/
13	cosmetic update	unneback	4953d 07h	/versatile_library/trunk/rtl/
12	added wishbone comliant modules	unneback	4954d 03h	/versatile_library/trunk/rtl/
11	async fifo simplex	unneback	4954d 18h	/versatile_library/trunk/rtl/
10	added dff_ce_clear	unneback	4956d 17h	/versatile_library/trunk/rtl/
8	added dff_ce_clear	unneback	4956d 17h	/versatile_library/trunk/rtl/
7	mem update	unneback	4956d 18h	/versatile_library/trunk/rtl/
6	added library files	unneback	4969d 18h	/versatile_library/trunk/rtl/
5	memories added	unneback	4969d 18h	/versatile_library/trunk/rtl/
4	added counters	unneback	4973d 22h	/versatile_library/trunk/rtl/
3	various updates counter added	unneback	4976d 17h	/versatile_library/trunk/rtl/
2	initial check-in	unneback	4977d 18h	/versatile_library/trunk/rtl/

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Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] - Rev 27

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