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[/] [versatile_library/] [trunk/] [rtl/] - Rev 32

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Rev Log message Author Age Path
32 added vl_pll for ALTERA (cycloneIII) unneback 3820d 03h /versatile_library/trunk/rtl/
31 sync FIFO updated unneback 3839d 23h /versatile_library/trunk/rtl/
30 updated counter for level1 and level2 function unneback 3839d 23h /versatile_library/trunk/rtl/
29 updated counter for level1 and level2 function unneback 3839d 23h /versatile_library/trunk/rtl/
28 added sync simplex FIFO unneback 3841d 00h /versatile_library/trunk/rtl/
27 added sync simplex FIFO unneback 3841d 00h /versatile_library/trunk/rtl/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3841d 02h /versatile_library/trunk/rtl/
25 added sync FIFO unneback 3841d 15h /versatile_library/trunk/rtl/
24 added vl_dff_ce_set unneback 3842d 23h /versatile_library/trunk/rtl/
23 fixed port map error in async fifo 1r1w unneback 3843d 14h /versatile_library/trunk/rtl/
22 added binary counters unneback 3843d 19h /versatile_library/trunk/rtl/
21 reg -> wire in and or mux in logic unneback 3844d 15h /versatile_library/trunk/rtl/
18 naming convention vl_ unneback 3846d 02h /versatile_library/trunk/rtl/
17 unneback 3909d 15h /versatile_library/trunk/rtl/
15 added delay line unneback 3915d 23h /versatile_library/trunk/rtl/
14 reg -> wire for various signals unneback 3916d 04h /versatile_library/trunk/rtl/
13 cosmetic update unneback 3916d 06h /versatile_library/trunk/rtl/
12 added wishbone comliant modules unneback 3917d 02h /versatile_library/trunk/rtl/
11 async fifo simplex unneback 3917d 17h /versatile_library/trunk/rtl/
10 added dff_ce_clear unneback 3919d 15h /versatile_library/trunk/rtl/

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