URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 23

Rev	Log message	Author	Age	Path
23	fixed port map error in async fifo 1r1w	unneback	4745d 09h	/versatile_library/trunk/rtl/verilog/
22	added binary counters	unneback	4745d 14h	/versatile_library/trunk/rtl/verilog/
21	reg -> wire in and or mux in logic	unneback	4746d 10h	/versatile_library/trunk/rtl/verilog/
18	naming convention vl_	unneback	4747d 21h	/versatile_library/trunk/rtl/verilog/
17		unneback	4811d 11h	/versatile_library/trunk/rtl/verilog/
15	added delay line	unneback	4817d 18h	/versatile_library/trunk/rtl/verilog/
14	reg -> wire for various signals	unneback	4818d 00h	/versatile_library/trunk/rtl/verilog/
13	cosmetic update	unneback	4818d 01h	/versatile_library/trunk/rtl/verilog/
12	added wishbone comliant modules	unneback	4818d 21h	/versatile_library/trunk/rtl/verilog/
11	async fifo simplex	unneback	4819d 12h	/versatile_library/trunk/rtl/verilog/
10	added dff_ce_clear	unneback	4821d 11h	/versatile_library/trunk/rtl/verilog/
8	added dff_ce_clear	unneback	4821d 11h	/versatile_library/trunk/rtl/verilog/
7	mem update	unneback	4821d 12h	/versatile_library/trunk/rtl/verilog/
6	added library files	unneback	4834d 12h	/versatile_library/trunk/rtl/verilog/
5	memories added	unneback	4834d 13h	/versatile_library/trunk/rtl/verilog/
4	added counters	unneback	4838d 16h	/versatile_library/trunk/rtl/verilog/
3	various updates counter added	unneback	4841d 12h	/versatile_library/trunk/rtl/verilog/
2	initial check-in	unneback	4842d 12h	/versatile_library/trunk/rtl/verilog/