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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 25

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Rev Log message Author Age Path
25 added sync FIFO unneback 3936d 03h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 3937d 10h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 3938d 01h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 3938d 06h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 3939d 02h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 3940d 13h /versatile_library/trunk/rtl/verilog/
17 unneback 4004d 03h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4010d 10h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4010d 16h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 4010d 17h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 4011d 13h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 4012d 04h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 4014d 03h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 4014d 03h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 4014d 04h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 4027d 04h /versatile_library/trunk/rtl/verilog/
5 memories added unneback 4027d 05h /versatile_library/trunk/rtl/verilog/
4 added counters unneback 4031d 08h /versatile_library/trunk/rtl/verilog/
3 various updates
counter added
unneback 4034d 04h /versatile_library/trunk/rtl/verilog/
2 initial check-in unneback 4035d 04h /versatile_library/trunk/rtl/verilog/

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