OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 26

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4852d 03h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4852d 17h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4854d 00h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4854d 15h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4854d 20h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4855d 16h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4857d 04h /versatile_library/trunk/rtl/verilog/
17 unneback 4920d 17h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4927d 01h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4927d 06h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 4927d 07h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 4928d 03h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 4928d 18h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 4930d 17h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 4930d 17h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 4930d 18h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 4943d 18h /versatile_library/trunk/rtl/verilog/
5 memories added unneback 4943d 19h /versatile_library/trunk/rtl/verilog/
4 added counters unneback 4947d 23h /versatile_library/trunk/rtl/verilog/
3 various updates
counter added
unneback 4950d 18h /versatile_library/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.