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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 28

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Rev Log message Author Age Path
28 added sync simplex FIFO unneback 4879d 11h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 4879d 11h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4879d 12h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4880d 02h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4881d 09h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4882d 00h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4882d 05h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4883d 01h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4884d 12h /versatile_library/trunk/rtl/verilog/
17 unneback 4948d 02h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4954d 09h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4954d 15h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 4954d 16h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 4955d 12h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 4956d 03h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 4958d 02h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 4958d 02h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 4958d 03h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 4971d 03h /versatile_library/trunk/rtl/verilog/
5 memories added unneback 4971d 04h /versatile_library/trunk/rtl/verilog/
4 added counters unneback 4975d 07h /versatile_library/trunk/rtl/verilog/
3 various updates
counter added		 unneback 4978d 03h /versatile_library/trunk/rtl/verilog/
2 initial check-in unneback 4979d 03h /versatile_library/trunk/rtl/verilog/

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