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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 29

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Rev Log message Author Age Path
29 updated counter for level1 and level2 function unneback 4851d 04h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4852d 05h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 4852d 05h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4852d 06h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4852d 20h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4854d 04h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4854d 18h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4854d 23h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4855d 20h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4857d 07h /versatile_library/trunk/rtl/verilog/
17 unneback 4920d 20h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4927d 04h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4927d 09h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 4927d 10h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 4928d 06h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 4928d 21h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 4930d 20h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 4930d 20h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 4930d 21h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 4943d 22h /versatile_library/trunk/rtl/verilog/
5 memories added unneback 4943d 22h /versatile_library/trunk/rtl/verilog/
4 added counters unneback 4948d 02h /versatile_library/trunk/rtl/verilog/
3 various updates
counter added
unneback 4950d 21h /versatile_library/trunk/rtl/verilog/
2 initial check-in unneback 4951d 21h /versatile_library/trunk/rtl/verilog/

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