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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 32

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Rev Log message Author Age Path
32 added vl_pll for ALTERA (cycloneIII) unneback 3812d 00h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 3831d 19h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 3831d 20h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 3831d 20h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 3832d 21h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 3832d 21h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3832d 22h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 3833d 12h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 3834d 19h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 3835d 10h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 3835d 15h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 3836d 11h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 3837d 23h /versatile_library/trunk/rtl/verilog/
17 unneback 3901d 12h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 3907d 20h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 3908d 01h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 3908d 02h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 3908d 22h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 3909d 13h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 3911d 12h /versatile_library/trunk/rtl/verilog/

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