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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 32

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Rev Log message Author Age Path
32 added vl_pll for ALTERA (cycloneIII) unneback 3984d 16h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 4004d 12h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 4004d 12h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 4004d 12h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4005d 13h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 4005d 13h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4005d 15h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4006d 04h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4007d 12h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4008d 03h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4008d 08h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4009d 04h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4010d 15h /versatile_library/trunk/rtl/verilog/
17 unneback 4074d 04h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4080d 12h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4080d 17h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 4080d 19h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 4081d 15h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 4082d 06h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 4084d 04h /versatile_library/trunk/rtl/verilog/

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