OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 32

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
32 added vl_pll for ALTERA (cycloneIII) unneback 3618d 00h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 3637d 20h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 3637d 20h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 3637d 20h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 3638d 21h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 3638d 21h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3638d 23h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 3639d 12h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 3640d 20h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 3641d 11h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 3641d 16h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 3642d 12h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 3643d 23h /versatile_library/trunk/rtl/verilog/
17 unneback 3707d 12h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 3713d 20h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 3714d 01h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 3714d 03h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 3714d 23h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 3715d 14h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 3717d 12h /versatile_library/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.