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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 32

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Rev Log message Author Age Path
32 added vl_pll for ALTERA (cycloneIII) unneback 4853d 06h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 4873d 01h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 4873d 02h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 4873d 02h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4874d 03h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 4874d 03h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4874d 04h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4874d 18h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4876d 01h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4876d 16h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4876d 21h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4877d 17h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4879d 05h /versatile_library/trunk/rtl/verilog/
17 unneback 4942d 18h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4949d 02h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4949d 07h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 4949d 08h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 4950d 04h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 4950d 19h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 4952d 18h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 4952d 18h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 4952d 19h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 4965d 19h /versatile_library/trunk/rtl/verilog/
5 memories added unneback 4965d 20h /versatile_library/trunk/rtl/verilog/
4 added counters unneback 4969d 23h /versatile_library/trunk/rtl/verilog/
3 various updates
counter added		 unneback 4972d 19h /versatile_library/trunk/rtl/verilog/
2 initial check-in unneback 4973d 19h /versatile_library/trunk/rtl/verilog/

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