OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 34

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
34 added vl_mux2_andor and vl_mux3_andor unneback 4837d 10h /versatile_library/trunk/rtl/verilog/
33 updated wb3wb3_bridge unneback 4850d 12h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 4857d 22h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 4877d 18h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 4877d 18h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 4877d 18h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4878d 19h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 4878d 19h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4878d 21h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4879d 10h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4880d 18h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4881d 09h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4881d 14h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4882d 10h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4883d 21h /versatile_library/trunk/rtl/verilog/
17 unneback 4947d 10h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4953d 18h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4953d 23h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 4954d 01h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 4954d 21h /versatile_library/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.