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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 36

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Rev Log message Author Age Path
36 added generic andor_mux unneback 4831d 15h /versatile_library/trunk/rtl/verilog/
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4832d 02h /versatile_library/trunk/rtl/verilog/
34 added vl_mux2_andor and vl_mux3_andor unneback 4832d 02h /versatile_library/trunk/rtl/verilog/
33 updated wb3wb3_bridge unneback 4845d 04h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 4852d 14h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 4872d 09h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 4872d 10h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 4872d 10h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4873d 11h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 4873d 11h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4873d 12h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4874d 02h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4875d 10h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4876d 00h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4876d 06h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4877d 02h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4878d 13h /versatile_library/trunk/rtl/verilog/
17 unneback 4942d 02h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4948d 10h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4948d 15h /versatile_library/trunk/rtl/verilog/

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