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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 37

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Rev Log message Author Age Path
14 reg -> wire for various signals unneback 4927d 23h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 4928d 01h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 4928d 21h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 4929d 12h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 4931d 11h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 4931d 11h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 4931d 12h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 4944d 12h /versatile_library/trunk/rtl/verilog/
5 memories added unneback 4944d 12h /versatile_library/trunk/rtl/verilog/
4 added counters unneback 4948d 16h /versatile_library/trunk/rtl/verilog/

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