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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 41

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Rev Log message Author Age Path
41 typo in registers.v unneback 3824d 09h /versatile_library/trunk/rtl/verilog/
40 new build environment with custom.v added as a result file unneback 3824d 09h /versatile_library/trunk/rtl/verilog/
39 added simple port prio based wb arbiter unneback 3825d 06h /versatile_library/trunk/rtl/verilog/
38 updated andor mux unneback 3825d 06h /versatile_library/trunk/rtl/verilog/
37 corrected polynom with length 20 unneback 3831d 03h /versatile_library/trunk/rtl/verilog/
36 added generic andor_mux unneback 3832d 11h /versatile_library/trunk/rtl/verilog/
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 3832d 22h /versatile_library/trunk/rtl/verilog/
34 added vl_mux2_andor and vl_mux3_andor unneback 3832d 22h /versatile_library/trunk/rtl/verilog/
33 updated wb3wb3_bridge unneback 3846d 01h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 3853d 10h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 3873d 06h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 3873d 06h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 3873d 06h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 3874d 08h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 3874d 08h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3874d 09h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 3874d 22h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 3876d 06h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 3876d 21h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 3877d 02h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 3877d 22h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 3879d 09h /versatile_library/trunk/rtl/verilog/
17 unneback 3942d 22h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 3949d 06h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 3949d 11h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 3949d 13h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 3950d 09h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 3951d 00h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 3952d 23h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 3952d 23h /versatile_library/trunk/rtl/verilog/

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