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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 43

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Rev Log message Author Age Path
23 fixed port map error in async fifo 1r1w unneback 3532d 06h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 3532d 11h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 3533d 07h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 3534d 18h /versatile_library/trunk/rtl/verilog/
17 unneback 3598d 07h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 3604d 15h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 3604d 20h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 3604d 22h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 3605d 18h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 3606d 09h /versatile_library/trunk/rtl/verilog/

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