OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 45

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
45 updated timing in io models unneback 4817d 01h /versatile_library/trunk/rtl/verilog/
44 added target independet IO functionns unneback 4820d 01h /versatile_library/trunk/rtl/verilog/
43 added logic for parity generation and check unneback 4824d 04h /versatile_library/trunk/rtl/verilog/
42 updated mux_andor unneback 4828d 04h /versatile_library/trunk/rtl/verilog/
41 typo in registers.v unneback 4828d 05h /versatile_library/trunk/rtl/verilog/
40 new build environment with custom.v added as a result file unneback 4828d 05h /versatile_library/trunk/rtl/verilog/
39 added simple port prio based wb arbiter unneback 4829d 02h /versatile_library/trunk/rtl/verilog/
38 updated andor mux unneback 4829d 03h /versatile_library/trunk/rtl/verilog/
37 corrected polynom with length 20 unneback 4834d 23h /versatile_library/trunk/rtl/verilog/
36 added generic andor_mux unneback 4836d 07h /versatile_library/trunk/rtl/verilog/
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4836d 19h /versatile_library/trunk/rtl/verilog/
34 added vl_mux2_andor and vl_mux3_andor unneback 4836d 19h /versatile_library/trunk/rtl/verilog/
33 updated wb3wb3_bridge unneback 4849d 21h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 4857d 07h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 4877d 02h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 4877d 02h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 4877d 02h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4878d 04h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 4878d 04h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4878d 05h /versatile_library/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.