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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 46

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Rev Log message Author Age Path
46 updated parity unneback 5198d 23h /versatile_library/trunk/rtl/verilog/
45 updated timing in io models unneback 5200d 17h /versatile_library/trunk/rtl/verilog/
44 added target independet IO functionns unneback 5203d 17h /versatile_library/trunk/rtl/verilog/
43 added logic for parity generation and check unneback 5207d 20h /versatile_library/trunk/rtl/verilog/
42 updated mux_andor unneback 5211d 20h /versatile_library/trunk/rtl/verilog/
41 typo in registers.v unneback 5211d 21h /versatile_library/trunk/rtl/verilog/
40 new build environment with custom.v added as a result file unneback 5211d 21h /versatile_library/trunk/rtl/verilog/
39 added simple port prio based wb arbiter unneback 5212d 18h /versatile_library/trunk/rtl/verilog/
38 updated andor mux unneback 5212d 19h /versatile_library/trunk/rtl/verilog/
37 corrected polynom with length 20 unneback 5218d 15h /versatile_library/trunk/rtl/verilog/
36 added generic andor_mux unneback 5219d 23h /versatile_library/trunk/rtl/verilog/
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 5220d 11h /versatile_library/trunk/rtl/verilog/
34 added vl_mux2_andor and vl_mux3_andor unneback 5220d 11h /versatile_library/trunk/rtl/verilog/
33 updated wb3wb3_bridge unneback 5233d 13h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 5240d 23h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 5260d 18h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 5260d 18h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 5260d 18h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 5261d 20h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 5261d 20h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5261d 21h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 5262d 11h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 5263d 18h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 5264d 09h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 5264d 14h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 5265d 10h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 5266d 21h /versatile_library/trunk/rtl/verilog/
17 unneback 5330d 11h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 5336d 18h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 5337d 00h /versatile_library/trunk/rtl/verilog/

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