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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 46

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Rev Log message Author Age Path
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4852d 20h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4853d 09h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4854d 17h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4855d 07h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4855d 13h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4856d 09h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4857d 20h /versatile_library/trunk/rtl/verilog/
17 unneback 4921d 09h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4927d 17h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4927d 22h /versatile_library/trunk/rtl/verilog/

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