URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 48

Rev	Log message	Author	Age	Path
27	added sync simplex FIFO	unneback	4871d 07h	/versatile_library/trunk/rtl/verilog/
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4871d 08h	/versatile_library/trunk/rtl/verilog/
25	added sync FIFO	unneback	4871d 22h	/versatile_library/trunk/rtl/verilog/
24	added vl_dff_ce_set	unneback	4873d 06h	/versatile_library/trunk/rtl/verilog/
23	fixed port map error in async fifo 1r1w	unneback	4873d 20h	/versatile_library/trunk/rtl/verilog/
22	added binary counters	unneback	4874d 01h	/versatile_library/trunk/rtl/verilog/
21	reg -> wire in and or mux in logic	unneback	4874d 21h	/versatile_library/trunk/rtl/verilog/
18	naming convention vl_	unneback	4876d 09h	/versatile_library/trunk/rtl/verilog/
17		unneback	4939d 22h	/versatile_library/trunk/rtl/verilog/
15	added delay line	unneback	4946d 06h	/versatile_library/trunk/rtl/verilog/