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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 49

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Rev Log message Author Age Path
49 added WB_B4RAM with byte enable unneback 4708d 12h /versatile_library/trunk/rtl/verilog/
48 wb updated unneback 4715d 06h /versatile_library/trunk/rtl/verilog/
46 updated parity unneback 4811d 11h /versatile_library/trunk/rtl/verilog/
45 updated timing in io models unneback 4813d 05h /versatile_library/trunk/rtl/verilog/
44 added target independet IO functionns unneback 4816d 05h /versatile_library/trunk/rtl/verilog/
43 added logic for parity generation and check unneback 4820d 08h /versatile_library/trunk/rtl/verilog/
42 updated mux_andor unneback 4824d 08h /versatile_library/trunk/rtl/verilog/
41 typo in registers.v unneback 4824d 10h /versatile_library/trunk/rtl/verilog/
40 new build environment with custom.v added as a result file unneback 4824d 10h /versatile_library/trunk/rtl/verilog/
39 added simple port prio based wb arbiter unneback 4825d 07h /versatile_library/trunk/rtl/verilog/
38 updated andor mux unneback 4825d 07h /versatile_library/trunk/rtl/verilog/
37 corrected polynom with length 20 unneback 4831d 03h /versatile_library/trunk/rtl/verilog/
36 added generic andor_mux unneback 4832d 12h /versatile_library/trunk/rtl/verilog/
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4832d 23h /versatile_library/trunk/rtl/verilog/
34 added vl_mux2_andor and vl_mux3_andor unneback 4832d 23h /versatile_library/trunk/rtl/verilog/
33 updated wb3wb3_bridge unneback 4846d 01h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 4853d 11h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 4873d 06h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 4873d 07h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 4873d 07h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4874d 08h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 4874d 08h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4874d 09h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4874d 23h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4876d 07h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4876d 21h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4877d 02h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4877d 23h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4879d 10h /versatile_library/trunk/rtl/verilog/
17 unneback 4942d 23h /versatile_library/trunk/rtl/verilog/

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