URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 67

Rev	Log message	Author	Age	Path
46	updated parity	unneback	4815d 03h	/versatile_library/trunk/rtl/verilog/
45	updated timing in io models	unneback	4816d 21h	/versatile_library/trunk/rtl/verilog/
44	added target independet IO functionns	unneback	4819d 21h	/versatile_library/trunk/rtl/verilog/
43	added logic for parity generation and check	unneback	4824d 00h	/versatile_library/trunk/rtl/verilog/
42	updated mux_andor	unneback	4828d 00h	/versatile_library/trunk/rtl/verilog/
41	typo in registers.v	unneback	4828d 01h	/versatile_library/trunk/rtl/verilog/
40	new build environment with custom.v added as a result file	unneback	4828d 01h	/versatile_library/trunk/rtl/verilog/
39	added simple port prio based wb arbiter	unneback	4828d 22h	/versatile_library/trunk/rtl/verilog/
38	updated andor mux	unneback	4828d 22h	/versatile_library/trunk/rtl/verilog/
37	corrected polynom with length 20	unneback	4834d 19h	/versatile_library/trunk/rtl/verilog/