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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 70

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Rev Log message Author Age Path
50 added WB_B4RAM with byte enable unneback 4887d 07h /versatile_library/trunk/rtl/verilog/
49 added WB_B4RAM with byte enable unneback 4887d 07h /versatile_library/trunk/rtl/verilog/
48 wb updated unneback 4894d 01h /versatile_library/trunk/rtl/verilog/
46 updated parity unneback 4990d 06h /versatile_library/trunk/rtl/verilog/
45 updated timing in io models unneback 4992d 00h /versatile_library/trunk/rtl/verilog/
44 added target independet IO functionns unneback 4995d 00h /versatile_library/trunk/rtl/verilog/
43 added logic for parity generation and check unneback 4999d 03h /versatile_library/trunk/rtl/verilog/
42 updated mux_andor unneback 5003d 03h /versatile_library/trunk/rtl/verilog/
41 typo in registers.v unneback 5003d 04h /versatile_library/trunk/rtl/verilog/
40 new build environment with custom.v added as a result file unneback 5003d 04h /versatile_library/trunk/rtl/verilog/

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