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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 90

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Rev Log message Author Age Path
90 updated wishbone byte enable mem unneback 3803d 15h /versatile_library/trunk/rtl/verilog/
86 wb ram unneback 3804d 10h /versatile_library/trunk/rtl/verilog/
85 wb ram unneback 3804d 11h /versatile_library/trunk/rtl/verilog/
84 wb ram unneback 3804d 11h /versatile_library/trunk/rtl/verilog/
83 new BE_RAM unneback 3804d 22h /versatile_library/trunk/rtl/verilog/
82 read changed to comb unneback 3805d 20h /versatile_library/trunk/rtl/verilog/
81 read changed to comb unneback 3805d 20h /versatile_library/trunk/rtl/verilog/
80 avalon read write unneback 3808d 16h /versatile_library/trunk/rtl/verilog/
79 avalon read write unneback 3808d 16h /versatile_library/trunk/rtl/verilog/
78 default to length = 1 unneback 3808d 17h /versatile_library/trunk/rtl/verilog/
77 bridge update unneback 3808d 19h /versatile_library/trunk/rtl/verilog/
76 dependency for wb3 to avalon bus unneback 3808d 22h /versatile_library/trunk/rtl/verilog/
75 added wb to avalon bridge unneback 3808d 22h /versatile_library/trunk/rtl/verilog/
73 no arbiter in wb_b3_ram_be unneback 3816d 20h /versatile_library/trunk/rtl/verilog/
72 no arbiter in wb_b3_ram_be unneback 3816d 20h /versatile_library/trunk/rtl/verilog/
71 no arbiter in wb_b3_ram_be unneback 3816d 20h /versatile_library/trunk/rtl/verilog/
70 no arbiter in wb_b3_ram_be unneback 3816d 20h /versatile_library/trunk/rtl/verilog/
69 no arbiter in wb_b3_ram_be unneback 3816d 20h /versatile_library/trunk/rtl/verilog/
68 ram_be updated to optional mem_size unneback 3816d 20h /versatile_library/trunk/rtl/verilog/
67 support up to 8 wbm on arbiter unneback 3817d 20h /versatile_library/trunk/rtl/verilog/
66 RAM_BE ack_o vector unneback 3855d 19h /versatile_library/trunk/rtl/verilog/
65 RAM_BE system verilog version unneback 3855d 19h /versatile_library/trunk/rtl/verilog/
64 SPR reset value unneback 3855d 20h /versatile_library/trunk/rtl/verilog/
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3855d 20h /versatile_library/trunk/rtl/verilog/
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3855d 20h /versatile_library/trunk/rtl/verilog/
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3855d 20h /versatile_library/trunk/rtl/verilog/
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3857d 16h /versatile_library/trunk/rtl/verilog/
59 added WB RAM B3 with byte enable unneback 3858d 16h /versatile_library/trunk/rtl/verilog/
58 corrected EXT unit, rewrite of FF1, FL1 unneback 3874d 22h /versatile_library/trunk/rtl/verilog/
57 corrected EXT unit, rewrite of FF1, FL1 unneback 3874d 22h /versatile_library/trunk/rtl/verilog/

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