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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 146

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139 unneback 4710d 11h /versatile_library/trunk/rtl/verilog/Makefile
75 added wb to avalon bridge unneback 4804d 21h /versatile_library/trunk/rtl/verilog/Makefile
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4853d 14h /versatile_library/trunk/rtl/verilog/Makefile
44 added target independet IO functionns unneback 4993d 13h /versatile_library/trunk/rtl/verilog/Makefile
40 new build environment with custom.v added as a result file unneback 5001d 18h /versatile_library/trunk/rtl/verilog/Makefile
33 updated wb3wb3_bridge unneback 5023d 09h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 5050d 15h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5051d 18h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 5052d 07h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 5054d 11h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 5056d 18h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 5127d 18h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 5143d 10h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 5147d 13h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 5150d 08h /versatile_library/trunk/rtl/verilog/Makefile

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