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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 147

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139 unneback 3295d 00h /versatile_library/trunk/rtl/verilog/Makefile
75 added wb to avalon bridge unneback 3389d 10h /versatile_library/trunk/rtl/verilog/Makefile
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3438d 03h /versatile_library/trunk/rtl/verilog/Makefile
44 added target independet IO functionns unneback 3578d 02h /versatile_library/trunk/rtl/verilog/Makefile
40 new build environment with custom.v added as a result file unneback 3586d 07h /versatile_library/trunk/rtl/verilog/Makefile
33 updated wb3wb3_bridge unneback 3607d 22h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 3635d 04h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3636d 07h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 3636d 20h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 3639d 00h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 3641d 07h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 3712d 07h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 3727d 22h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 3732d 02h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 3734d 21h /versatile_library/trunk/rtl/verilog/Makefile

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