OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 153

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
139 unneback 2918d 05h /versatile_library/trunk/rtl/verilog/Makefile
75 added wb to avalon bridge unneback 3012d 15h /versatile_library/trunk/rtl/verilog/Makefile
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3061d 09h /versatile_library/trunk/rtl/verilog/Makefile
44 added target independet IO functionns unneback 3201d 08h /versatile_library/trunk/rtl/verilog/Makefile
40 new build environment with custom.v added as a result file unneback 3209d 13h /versatile_library/trunk/rtl/verilog/Makefile
33 updated wb3wb3_bridge unneback 3231d 04h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 3258d 10h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3259d 12h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 3260d 02h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 3262d 06h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 3264d 13h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 3335d 13h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 3351d 04h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 3355d 08h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 3358d 03h /versatile_library/trunk/rtl/verilog/Makefile

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.