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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 72

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Rev Log message Author Age Path
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3864d 06h /versatile_library/trunk/rtl/verilog/Makefile
44 added target independet IO functionns unneback 4004d 05h /versatile_library/trunk/rtl/verilog/Makefile
40 new build environment with custom.v added as a result file unneback 4012d 10h /versatile_library/trunk/rtl/verilog/Makefile
33 updated wb3wb3_bridge unneback 4034d 01h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 4061d 07h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4062d 09h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 4062d 23h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 4065d 03h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 4067d 10h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 4138d 10h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 4154d 01h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 4158d 05h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 4161d 00h /versatile_library/trunk/rtl/verilog/Makefile

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