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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 75

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75 added wb to avalon bridge unneback 3075d 03h /versatile_library/trunk/rtl/verilog/Makefile
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3123d 21h /versatile_library/trunk/rtl/verilog/Makefile
44 added target independet IO functionns unneback 3263d 20h /versatile_library/trunk/rtl/verilog/Makefile
40 new build environment with custom.v added as a result file unneback 3272d 01h /versatile_library/trunk/rtl/verilog/Makefile
33 updated wb3wb3_bridge unneback 3293d 16h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 3320d 22h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3322d 01h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 3322d 14h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 3324d 18h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 3327d 01h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 3398d 01h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 3413d 16h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 3417d 20h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 3420d 15h /versatile_library/trunk/rtl/verilog/Makefile

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