OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 86

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
75 added wb to avalon bridge unneback 4605d 01h /versatile_library/trunk/rtl/verilog/Makefile
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4653d 18h /versatile_library/trunk/rtl/verilog/Makefile
44 added target independet IO functionns unneback 4793d 18h /versatile_library/trunk/rtl/verilog/Makefile
40 new build environment with custom.v added as a result file unneback 4801d 23h /versatile_library/trunk/rtl/verilog/Makefile
33 updated wb3wb3_bridge unneback 4823d 14h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 4850d 19h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4851d 22h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 4852d 12h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 4854d 15h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 4856d 22h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 4927d 22h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 4943d 14h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 4947d 17h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 4950d 13h /versatile_library/trunk/rtl/verilog/Makefile

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.