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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Rev 112

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Rev Log message Author Age Path
48 wb updated unneback 3364d 08h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
40 new build environment with custom.v added as a result file unneback 3473d 12h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
33 updated wb3wb3_bridge unneback 3495d 03h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3502d 13h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
21 reg -> wire in and or mux in logic unneback 3527d 00h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
18 naming convention vl_ unneback 3528d 11h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
17 unneback 3592d 01h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
4 added counters unneback 3619d 06h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
3 various updates
counter added
unneback 3622d 02h /versatile_library/trunk/rtl/verilog/clk_and_reset.v

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